The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design, and nanometer technology have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs, but also increased the complexity of processing and manufacturing ICs and casted challenges from both fabrication and design issues.
Generally, an integrated circuit (IC) manufacturing comprises largely a “data preparation stage” where an IC to be fabricated is designed to produce an IC layout, and a “fabrication stage,” where the ICs are fabricated according to the designed layout in a fab house. The fabrication stage includes largely, a photomask generation, a wafer preparation, and a wafer processing, wafer test, die preparation, and packaging that ends up with a finished chip that comprises up to eleven metal levels in modern days. The wafer processing itself, which produces the desired semiconductor electronic elements on the wafer, comprises over 300 sequenced line of processes that are largely divided into a front-end of line processing such as deposition, removal, patterning, and ion doping, and a back-end of line processing such as creating metal interconnecting wires that are isolated by dielectric layers,
Once the various semiconductor devices have been created, they must be interconnected to form the desired electrical circuits. Traditionally, aluminum was the metal used for the interconnecting wire wherein films of aluminum are deposited, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires for insulation. The traditional insulating material was a form of silicon dioxides (SiO2) or a silicate glass. The various metal layers in a chip are interconnected by etching holes, called vias formed in the insulating material and filled with tungsten deposited therein by a CVD technique.
Recently, however, as the number of interconnect levels for logic substantially increased due to the large number of transistors interconnected in a modern microprocessor, the timing delay in the wiring, represented by the time constant RC (R: resistance, C: capacitance), has become significant. The need to reduce RC prompted a change both in wiring material and in dielectric material. For wiring material, copper came to replace aluminum in higher performance processors for its lower value of R, so a greater conductivity, than aluminum. For dielectric material, the SiO2 came to be replaced, for producing a greater C, by a new dielectric material having a low dielectric constant (“k”), such as SiOC (silicon oxycarbide) that has k around 2.7 as compared to 3.9 for SiO2. These days, even materials with ultra-low k of 2.2, are being offered to chipmakers.
The interconnecting wires are formed after the creation of semiconductor devices, such as MOSFETs or DRAMs, by a series of usual processes such as patterning, deposition, and etching. But in the current fabrication methods practiced in the art, which use a couple of processes of etching, there is observed a problem that the low k material becomes damaged by the etching process. In many cases, the etching process changes the k to a higher value, thereby destroying the benefit of improved RC value and impairing the reliability of the performance expected from the use of the low k dielectrics.
Therefore, there is a need to provide a method for forming interconnecting wires in fabricating semiconductor device, using copper and low k dielectric materials, where the low k dielectric material is protected from damage due to etching processes to ensure improved interconnect time delay and reliability of performance.